IBM develops 7A NanoStack transistor technology to improve semiconductor density

IBM has introduced a new 7-angstrom (0.7-nanometer) NanoStack transistor technology, which the company claims significantly advances semiconductor scaling. This architecture utilizes a staggered, sequential complementary field-effect transistor (CFET) design, which involves bonding two wafers to stack transistors vertically rather than placing them side-by-side. By integrating these components, IBM reports a 50% improvement in logic area scaling, 50% higher performance at equivalent power, 70% better efficiency at equivalent performance, and 40% SRAM scaling. The technology effectively doubles the number of transistors per square millimeter compared to previous 2-nanometer gate-all-around designs, reaching approximately 666 million transistors per square millimeter. The process relies on advanced wafer-to-wafer bonding and high-aspect-ratio etching to manage thermal and structural constraints. While IBM develops these process nodes, they function primarily as a research-focused entity that licenses these innovations to external foundries, which must then adapt the technology for high-volume manufacturing. The company notes that the critical innovation lies in the bonding oxide layer, which must be maintained at a thickness of 30 nanometers or less to ensure structural and electrical integrity.

IBM's 7A NanoStack technology utilizes a staggered, sequential CFET design to increase transistor density. The architecture achieves 50% logic area scaling and 50% performance gains at equivalent power levels.

The design enables a density of approximately 666 million transistors per square millimeter. The process relies on wafer-to-wafer bonding to stack N-type and P-type transistors vertically.

IBM maintains that the critical innovation is the bonding oxide layer, which must be under 30 nanometers thick. The technology is currently in the research phase and requires adaptation for high-volume manufacturing.