Intel details the architecture of its upcoming Diamond Rapids Xeon processor

Intel's upcoming Diamond Rapids Xeon processor, scheduled for 2027, utilizes a disaggregated, modular architecture designed for high-performance data center workloads. The CPU features a fan-out fabric architecture that connects four compute building blocks to two central fabric hubs. Each compute block contains four core chiplets, each with 16 cores, for a total of 256 cores. The base tile of each compute block holds 320MB of shared L3 cache, resulting in 1.28GB of total last-level cache. The fabric hubs manage memory and I/O, supporting 16 channels of DDR5-8000 or DDR5-12800 MRDIMM, and providing 128 lanes of PCIe Gen 6, CXL 3.0, and UPI 3.0. The design employs Intel 3 process nodes for the fabric hubs and 18A-P for the core chiplets, utilizing Foveros 3D Direct packaging. The architecture also introduces Intel Advanced Performance Extensions (APX), which adds new general-purpose registers and instructions to improve performance without requiring source code changes. The design prioritizes compute-bound workloads, allowing for dynamic power allocation between the memory controller and the cores.

Tech4K StaffVideo report

Intel's upcoming Diamond Rapids Xeon processor, scheduled for 2027, utilizes a disaggregated, modular architecture designed for high-performance data center workloads. The CPU features a fan-out fabric architecture that connects four compute building blocks to two central fabric hubs. Each compute block contains four core chiplets, each with 16 cores, for a total of 256 cores. The base tile of each compute block holds 320MB of shared L3 cache, resulting in 1.28GB of total last-level cache. The fabric hubs manage memory and I/O, supporting 16 channels of DDR5-8000 or DDR5-12800 MRDIMM, and providing 128 lanes of PCIe Gen 6, CXL 3.0, and UPI 3.0. The design employs Intel 3 process nodes for the fabric hubs and 18A-P for the core chiplets, utilizing Foveros 3D Direct packaging. The architecture also introduces Intel Advanced Performance Extensions (APX), which adds new general-purpose registers and instructions to improve performance without requiring source code changes. The design prioritizes compute-bound workloads, allowing for dynamic power allocation between the memory controller and the cores.

Diamond Rapids is a 2027-era Xeon processor featuring a modular, disaggregated architecture with up to 256 cores. The processor utilizes a fan-out fabric architecture to connect four compute building blocks to two central fabric hubs.

Each compute building block contains four 16-core chiplets and 320MB of shared L3 cache, totaling 1.28GB of L3 cache. The fabric hubs support 16 channels of high-speed DDR5 memory and 128 lanes of PCIe Gen 6 and CXL 3.0 connectivity.

Intel Advanced Performance Extensions (APX) are integrated to enhance performance by adding 16 new general-purpose registers. The chip is manufactured using Intel 3 process nodes for the fabric hubs and 18A-P for the core chiplets.

Chapter guide

IntroductionOverview of the Hot Chips presentation on Intel's Diamond Rapids Xeon CPU.Architecture EvolutionA look at the progression of Intel Xeon architectures from ring to 3D mesh.Fan-out Fabric ArchitectureExplanation of the new fabric design and compute building blocks.Memory and I/ODetails on the memory controller, CXL support, and high-speed I/O fabric.Power and Thermal ManagementDiscussion of the distinct DVFS domains and power-saving features.Construction and ProcessBreakdown of the manufacturing process nodes and 3D packaging technology.Advanced Performance ExtensionsIntroduction to Intel APX and its impact on performance.

Worth noting

  • Diamond Rapids is an unreleased product scheduled for 2027; specifications are subject to change.
  • The presentation is based on Intel's internal data and projections.
  • The host notes that the video is not sponsored by Intel.

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