NVIDIA has begun utilizing its custom Vera CPU architecture to streamline the development of its next generation of processors. By deploying these chips across its internal electronic design automation (EDA) workflows, the company aims to address the increasing complexity of modern semiconductor engineering, which requires extensive simulation, verification, and implementation cycles before a design reaches the manufacturing stage.
The Vera CPU is built with 88 custom NVIDIA Olympus cores, paired with an LPDDR5X memory subsystem and the company's second-generation Scalable Coherent Fabric. This hardware configuration is specifically engineered to provide high per-core performance, significant memory bandwidth, and low latency, which are critical requirements for the compute-intensive tasks involved in transforming register-transfer level (RTL) descriptions into finished silicon.
Initial testing conducted by NVIDIA in collaboration with industry partners Cadence and Synopsys has yielded performance gains of up to 1.5x on specific production-class workloads. The testing focused on Cadence Jasper, a formal verification platform that utilizes machine learning to identify bugs, and Synopsys VCS, a high-performance functional verification solution used to simulate complex chip designs prior to fabrication.
These improvements in verification throughput are intended to help engineering teams identify design issues earlier in the development cycle, thereby reducing the need for costly downstream iterations. By shortening individual verification runs and increasing overall throughput, the company expects to evaluate a greater number of design alternatives within existing development windows.
Looking toward future hardware iterations, NVIDIA has confirmed plans to succeed the Vera CPU with a next-generation processor named Rosa, which will be powered by the NVIDIA Rigel core. The company intends to continue optimizing EDA applications across its CPU roadmap, maintaining a feedback loop where its own silicon designs are used to accelerate the creation of subsequent generations of CPUs and GPUs.